A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation

This paper proposes a two-write and two-read (2W2R) bit-cell for a multi-port (MP) SRAM design to improve the static noise margin (SNM) and solve the write-disturb issues of nanoscale CMOS technologies. Using an additional Y -access MOS (column-direction access transistor), the 2W2R MP SRAM adopts a scheme of combining the row access transistor and sharing write bit-line with an adjacent bit cell. This scheme halves the write bit-line number and mitigates the write current consumption caused by pre-charging the bit-line to VDD. This paper also proposes a selective read path structure for read operation. Replacing the ground connection in the read port with a virtual VSS controlled by a Y -select signal reduces read-port current consumption. Results show that the proposed design reduces both the write current and read current consumption by 30%, compared to the conventional MP structure, from 1.3 V to 0.6 V VDD. The proposed 8 Kb 2W2R MP SRAM was fabricated on the test chip using TSMC 40 nm CMOS technology.